555

Do you mean the 555 timer IC? Here’s a compact refresher you can use for exams.

Pinout (NE555 typical)

• 1 GND
• 2 TRIG
• 3 OUT
• 4 RESET
• 5 CTRL
• 6 THR (threshold)
• 7 DIS (discharge)
• 8 VCC

How it works (high level)

• Two comparators feed an SR latch; the latch controls the output and the transistor on pin 7 discharges the timing capacitor.
• Trigger input (TRIG) > output state changes when TRIG voltage drops below 1/3 VCC.
• Threshold input (THR) > 2/3 VCC resets the latch.
• Control pin (5) can modulate the reference for filters/noise immunity; usually decoupled with 0.01 μF.
• Reset pin (4) resets the latch if held low; tie to VCC if unused.

Modes

• Astable (free-running)

  • No external trigger; produces a continuous square wave.
  • Timing determined by RA, RB, C.
  • Key formulas:
    • f ≈ 1.44 / ((RA + 2RB) C)
    • Th = 0.693 (RA + RB) C
    • Tl = 0.693 RB C
    • Duty cycle D = (RA + RB) / (RA + 2RB)
  • Tip: use a diode in parallel with RB if you want a duty cycle < 50%.

• Monostable (one-shot)

  • Triggered by a negative pulse on TRIG; outputs a single pulse.
  • Pulse width t ≈ 1.1 R C (R and C chosen to set the desired width).
  • After the pulse, the capacitor discharges through the discharge transistor.

• Bistable (flip-flop)

  • Acts like a latch; set/reset with external triggers.
  • No timing capacitor required for the basic operation (uses RC only if you want edge-triggered timing).

Common design notes

• Use a decoupling capacitor (e.g., 0.01 μF) on the control pin and a bypass capacitor (e.g., 0.1 μF) near VCC.
• Tie RESET to VCC if not used to prevent accidental resets.
• The NE555 can source/sink limited current; buffer the output if driving LEDs, transistors, or motors.
• CMOS variants (e.g., 7555, LMC555) operate at lower power and wider voltage ranges.

Example to illustrate

• Suppose RA = 1 kΩ, RB = 10 kΩ, C = 0.1 μF for an astable:
  • f ≈ 1.44 / ((1k + 2*10k) * 0.1e-6) = 1.44 / (21k * 0.1e-6) ≈ 1.44 / 0.0021 ≈ 685 Hz
  • Th ≈ 0.693 * (RA + RB) * C = 0.693 * 11k * 0.1e-6 ≈ 0.000762 s ≈ 0.76 ms
  • Tl ≈ 0.693 * RB * C = 0.693 * 10k * 0.1e-6 ≈ 0.000693 s ≈ 0.69 ms
  • Output duty cycle ≈ (RA + RB) / (RA + 2RB) ≈ 11k / 21k ≈ 52%

Would you like me to tailor this to a specific course (electrical engineering, digital electronics, etc.) or walk through a sample problem or schematic?