555

Here’s a quick 555 timer refresher you can use for exams. If you want, tell me a mode and I’ll make a worked example.

Pinout (8-pin DIP)

• Pin 1: GND
• Pin 2: Trigger
• Pin 3: Output
• Pin 4: Reset (active low)
• Pin 5: Control Voltage (usually a 0.01 µF cap to ground)
• Pin 6: Threshold
• Pin 7: Discharge
• Pin 8: Vcc

Key specs

• Supply range: typically 4.5 V to 15 V
• Internal comparators trip at 2/3 Vcc (threshold) and 1/3 Vcc (trigger)
• Can source/sink tens of mA (check your package)

Modes and formulae

1. Monostable (one-shot)

• How it works: A trigger pulse at pin 2 starts a timed output pulse. The timing is set by R and C.
• Timing equation: t ≈ 1.1 × R × C
• Typical wiring: Vcc -> R -> node -> C to ground; node also to threshold (pin 6) and discharge (pin 7) through the internal transistor; trigger (pin 2) pulls the node low to start timing.
• Notes: Reset (pin 4) should be held high if not used. Add a small cap on control pin (pin 5) if you need noise protection.

2. Astable (free-running oscillator)

• How it works: No trigger needed; the capacitor charges and discharges between 1/3 and 2/3 Vcc, producing a square wave.
• Timing equations:
  • t_high (output high) = 0.693 × (RA + RB) × C
  • t_low (output low) = 0.693 × RB × C
  • Frequency: f = 1 / (t_high + t_low) = 1.44 / [(RA + 2RB) × C]
  • Duty cycle: D = t_high / (t_high + t_low) = (RA + RB) / (RA + 2RB)
• Typical wiring: Vcc -> RA -> node -> RB -> discharge & threshold; capacitor C from node to ground; trigger not used (or tied to a fixed level).
• Notes: If you need a duty cycle less than 50%, you can add a diode across RB or use a design trick with a control voltage.

Practical tips

• Add decoupling: a small 0.01 µF (and maybe 0.1 µF) cap between Vcc and GND near the IC.
• Control voltage pin (5) can be used to modulate duty cycle (for PWM applications); otherwise tie to ground through a small cap.
• Real-world tolerances: resistor and capacitor tolerances change f and t. Expect ±5–20% variation depending on parts.
• Reset pin: keep high if unused; drive low to force a reset (output goes low).

Quick practice problems

1. Astable design Goal: f ≈ 1 kHz with C = 0.1 µF (100 nF). Choose RA and RB to get close.

• Use f = 1.44 / [(RA + 2RB) × C]
• Solve for (RA + 2RB): (RA + 2RB) = 1.44 / (f × C) = 1.44 / (1000 × 100e-9) = 1.44 / 0.0001 = 14.4k
• Pick RB = 5 kΩ, then RA = (14.4k − 2RB) = 14.4k − 10k = 4.4kΩ
• Approximate available standard values: RA ≈ 4.7 kΩ, RB ≈ 5.1 kΩ
• Resulting times: t_high ≈ 0.693 × (RA + RB) × C ≈ 0.693 × (4.7k + 5.1k) × 100 nF ≈ 0.693 × 9.8k × 100 nF ≈ 0.679 ms; t_low ≈ 0.693 × RB × C ≈ 0.693 × 5.1k × 100 nF ≈ 0.353 ms; f ≈ 1 kHz
• Duty cycle ≈ t_high / (t_high + t_low) ≈ 0.679 / (0.679 + 0.353) ≈ 0.658 → about 66%

2. Monostable timing Goal: Produce a single pulse of about 2 ms using a 555.

• Choose C = 100 µF, solve for R: t ≈ 1.1 × R × C → R ≈ t / (1.1 × C) = 2 ms / (1.1 × 100 µF) = 0.002 / 0.00011 ≈ 18.18 Ω? That looks off; check units.
• Correct approach: C = 100 µF = 100 × 10^-6 F. Then R ≈ 0.002 / (1.1 × 100×10^-6) = 0.002 / 0.00011 ≈ 18.18 Ω. That is too small for practical. So pick a smaller C or larger R.
• Example with sensible parts: If R = 10 kΩ, then C ≈ t / (1.1 × R) = 0.002 / (1.1 × 10000) ≈ 0.002 / 11000 ≈ 1.82 × 10^-7 F = 0.182 µF. Use C ≈ 0.18 µF (or 0.22 µF standard) to get near 2 ms.

If you want, tell me:

• Which mode you’re studying (monostable or astable),
• Your target frequency or pulse width,
• Any constraints on resistor/capacitor values, and I’ll tailor a worked example or design a circuit for you.