555

Are you asking about the 555 timer IC? Here’s a quick exam-ready refresher you can use.

Pinout (NE/LM version; CMOS variants similar)

• Pin 1: GND
• Pin 2: Trigger
• Pin 3: Output
• Pin 4: Reset (active low)
• Pin 5: Control Voltage (usually decoupled with 0.01 µF to ground)
• Pin 6: Threshold
• Pin 7: Discharge (transistor to ground)
• Pin 8: Vcc

How it works (basic idea)

• Two comparators compare the trigger to 1/3 Vcc and the threshold to 2/3 Vcc.
• Their outputs feed a set-reset latch; the latch drives the output and controls the discharge transistor.
• The output toggles based on trigger/threshold events; the discharge transistor quickly pulls the timing capacitor to ground when needed.

Modes and key formulas

1. Astable (free-running oscillator)

• No trigger needed; it continuously toggles.
• Timing: charging and discharging the timing capacitor C through resistors RA and RB.
• t_high = 0.693 (RA + RB) C
• t_low = 0.693 RB C
• Frequency: f = 1.44 / ((RA + 2RB) C)
• Duty cycle: D = (RA + RB) / (RA + 2RB) (range 50% to ~100%)

2. Monostable (one-shot)

• Trigger on pin 2 initiates a single pulse.
• Output goes high for t = 1.1 R C (R is the external resistor, C is the timing capacitor)
• After t, the output returns to low and waits for the next trigger.
• Trigger must go low to start (pulse width doesn’t matter beyond being a valid low).

3. Bistable (latch)

• Output toggles state with each trigger; reset can force a known state.
• No timing capacitor used for timing; used as a basic memory element.

Practical notes

• Supply range typically 4.5–15 V (some CMOS variants go lower/higher).
• Pin 5 often tied to ground through a 0.01 µF capacitor to reduce noise.
• Use decoupling capacitor close to Vcc and GND (e.g., 0.1 µF or 1 µF).
• Reset pin (4) should be tied high to enable operation; pull low to force a reset.
• CMOS versions (e.g., LMC555, TLC555) offer lower power and wider voltage range.

Quick example

• Design an astable with f ≈ 1 kHz, C = 10 nF.
  • Choose RA and RB so that (RA + 2RB) C ≈ 1.44 / f = 1.44 ms
  • (RA + 2RB) ≈ 1.44e-3 / 10e-9 = 144 kΩ
  • If RA = 40 kΩ, RB = 52 kΩ → RA + 2RB = 144 kΩ
  • t_high = 0.693 (RA + RB) C = 0.693 * (92 kΩ) * 10 nF ≈ 0.637 ms
  • t_low = 0.693 RB C = 0.693 * 52 kΩ * 10 nF ≈ 0.360 ms
  • f ≈ 1 / (t_high + t_low) ≈ 1 kHz
  • Duty ≈ (RA + RB) / (RA + 2RB) ≈ 92k / 144k ≈ 64%

Would you like more practice problems (e.g., compute resistor values for a target frequency, or design a specific timing interval), or a schematic exercise (draw the circuit for a monostable/astable)?