555

Do you mean the 555 timer IC? If so, here’s a quick exam-friendly refresher.

Key facts

• Pinout (8 pins): 1 GND, 2 TRIG, 3 OUT, 4 RESET, 5 CTRL, 6 THR, 7 DISCH, 8 VCC
• Internal blocks: two comparators (threshold 2/3 Vcc, trigger 1/3 Vcc), flip-flop, discharge transistor
• Modes:
  • Astable: free-running oscillator (no external trigger)
  • Monostable: one-shot pulse on trigger
  • Bistable (latch): toggles with SET/RESET pulses

Important thresholds

• Trigger threshold: 1/3 Vcc
• Threshold level: 2/3 Vcc
• Output behavior and discharge transistor change when these levels are crossed

Formulas and typical configurations

• Astable (no external trigger)
  • f ≈ 1.44 / ((RA + 2 RB) C)
  • High time TH ≈ 0.693 (RA + RB) C
  • Low time TL ≈ 0.693 RB C
  • Duty cycle D ≈ (RA + RB) / (RA + 2 RB)
  • Vcc range: typically 4.5 V to 15 V (depends on device)
• Monostable (one-shot)
  • Output high time T ≈ 1.1 R C
  • Trigger is a negative-going pulse shorter than T; when triggered, output goes high for T, then returns low
• Bistable
  • No timing components; output toggles with external SET and RESET inputs

Common values and tips

• Power: 4.5–15 V (TTL/CMOS variants exist)
• Input/output: usually TTL/CMOS compatible; output can drive LEDs or logic directly with appropriate current limiting
• Practical: add a small capacitor on CTRL pin (pin 5) to reduce noise (e.g., 10 nF)

Example design (1 kHz astable, Vcc = 5 V, C = 100 nF)

• Target f ≈ 1 kHz → RA + 2 RB ≈ 1.44 / (f C) = 1.44 / (1000 × 100 nF) ≈ 14.4 kΩ
• Choose standard values: RB = 5 kΩ, RA ≈ 4.4 kΩ (closest standard value 4.7 kΩ)
• Then f ≈ 1.44 / ((4.7k + 2×5k) × 100 nF) ≈ 1.0 kHz

What would you like?

• A quick one-page cheat sheet (pinout, modes, formulas)
• More worked practice problems (designing astable/monostable circuits)
• A specific exam-style question tailored to your course
• Clarify if you meant something else by “555” (e.g., a math problem, another context)