555

Not sure what you want with “555.” If you’re studying for electronics exams, here’s a concise quick-reference on the 555 timer IC (the NE555/LM555), including the two main operating modes and key formulas. If you meant something else, tell me and I’ll adjust.

Pinout (8-pin DIP)

• Pin 1: GND
• Pin 2: TRIG (trigger)
• Pin 3: OUT
• Pin 4: RESET (active low)
• Pin 5: CTRL (control voltage, typically 2/3 Vcc; often decoupled with a 0.01 µF cap)
• Pin 6: THR (threshold)
• Pin 7: DISCH (discharge transistor collector)
• Pin 8: VCC

Internal concept

• Two comparators detect 1/3 Vcc and 2/3 Vcc.
• A flip-flop drives the output.
• Discharge transistor pulls the timing capacitor to ground when RESET/FF states demand.
• Control voltage on CTRL pin shifts the trip levels (usually fixed at 1/3 and 2/3 of Vcc if CTRL is left open).

Two common modes

1. Monostable (one-shot)

• Trigger: A negative pulse on TRIG (< 1/3 Vcc) starts timing.
• Timing network: A resistor R (often just one resistor) and a timing capacitor C determine the pulse width.
• Timing formula: T ≈ 1.1 × R × C
  • Example: R = 10 kΩ, C = 100 nF → T ≈ 1.1 × 10k × 100nF ≈ 1.1 ms
• How it runs: Output goes high after trigger; the capacitor charges toward Vcc through R. When THR reaches 2/3 Vcc, the FF resets, output goes low, and the discharge transistor discharges C.

2. Astable (free-running oscillator)

• No external trigger; the circuit continuously triggers itself.
• Timing network: Two resistors R_A and R_B, and a capacitor C.
• Timing formulas:
  • T_high (output high) = 0.693 × (R_A + R_B) × C
  • T_low (output low) = 0.693 × R_B × C
  • Period T = T_high + T_low = 0.693 × (R_A + 2R_B) × C
  • Frequency f = 1 / T = 1 / [0.693 × (R_A + 2R_B) × C]
  • Duty cycle D = T_high / T = (R_A + R_B) / (R_A + 2R_B)
• How it runs: The capacitor charges through R_A + R_B toward Vcc and discharges through R_B via the discharge transistor to ground, repeatedly cycling between 1/3 Vcc and 2/3 Vcc.

Practical notes

• Decoupling: Place a 0.1 µF (and often a 1 µF) capacitor close to Vcc and GND.
• Reset pin: Tie RESET high (to Vcc) if not using it; a low on RESET forces the output low.
• Control pin: If you don’t need to modulate trip points, you can connect CTRL to a 2/3 Vcc reference and bypass with a small cap to ground.
• Output drive: The 555 can source/sink tens of mA, but for heavy loads use a buffer; for higher speed, consider CMOS variants (e.g., 7555/NE CMOS or LMC555).

Variants (quick mention)

• CMOS versions (e.g., 7555) use less current and operate differently at lower voltages.
• LMC555/LMV555 for low-voltage, low-power apps.
• All keep the same basic modes but with different thresholds and power specs.

Want practice problems or a deeper dive on a specific mode (monostable or astable) with example designs? Or is your course using a different timer model and you’d like a tailored derivation?