555

Do you mean the 555 timer IC, or something else (e.g., the number 555 or Roman numeral DLV)? If you’re studying the 555 timer for exams, here’s a concise cheat sheet you can use.

555 timer IC overview

• Type: 8-pin integrated timer/oscillator with comparators and a flip-flop.
• Pinout (typical):
  • 1: GND
  • 2: Trigger
  • 3: Output
  • 4: Reset (active low)
  • 5: Control Voltage (often with a 0.01 µF cap to ground)
  • 6: Threshold
  • 7: Discharge
  • 8: VCC

Modes of operation

• Monostable (one-shot)
  • Trigger on a negative edge at pin 2.
  • Output goes high for a time t, then returns to low.
  • t ≈ 1.1 × R × C (R is the resistor between VCC and the discharge/threshold node, C is the capacitor from that node to ground).
  • Reset must be kept high; holding Reset low forces Output low.
• Astable (oscillator)
  • No external trigger; output continuously switches between high and low.
  • Typical connections: R1 between VCC and pin 7 (Discharge); R2 between pin 7 and the timing node (pins 6/2); C from timing node to ground.
  • Frequency: f ≈ 1.44 / [(R1 + 2R2) × C]
  • Duty cycle: D ≈ (R1 + R2) / (R1 + 2R2)
  • Note: Default duty cycle is > 50%. For < 50%, use a diode to separate charge and discharge paths (or use a configuration with a transistor).
• Bistable (Schmitt, latch)
  • Two stable states; toggled by Trigger (pin 2) and Reset (pin 4).
  • No external timing capacitor required for basic operation; acts as a memory element.

Key operating notes

• Reset (pin 4) is active-low. Keeping it high allows normal operation; pulling it low forces Output low.
• Control Voltage (pin 5) sets the threshold for the internal comparators (usually tied to a 2/3 VCC reference). A small cap (e.g., 0.01–0.1 µF) to ground stabilizes it.
• Typical supply range: roughly 5–15 V (check your specific part; most common 555 timers tolerate up to 18 V).

Quick example problems

• Monostable: If R = 10 kΩ and C = 100 nF, t ≈ 1.1 × 10,000 × 100e-9 = 1.1 ms.
• Astable: Choose R1 = 1 kΩ, R2 = 10 kΩ, C = 100 nF.
  • f ≈ 1.44 / [(1k + 2×10k) × 100e-9] ≈ 1.44 / (21k × 100e-9) ≈ 685 Hz.
  • Duty cycle ≈ (1k + 10k) / (1k + 2×10k) ≈ 11k / 21k ≈ 52%.

If you want, I can walk through a specific design problem (e.g., design a 0.5 s monostable pulse or a 1 kHz astable with a given duty cycle) or answer a short set of practice questions. Do you want a worked example?